Gabriel @dss_gabriel
PhD candidate, HPC @ CEA. Architecture, distributed computing, memory management & data layout. RTFM 👹 github.com/dssgabriel France Joined April 2014-
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models such as cuTILE are *explicitly* meant to break away from the non fit for purpose model/memory semantics implied by the legacy cuda. it's why, while in PTX/SASS you can expose things like cache level DMA between SM's, you could never (practically) expose that model....
When an article about hpc/optimization is called "anatomy of" then you know the authors know their shit. For those who don't know, this is basically HPC's "attention is all you need" but less overcooked:
When an article about hpc/optimization is called "anatomy of" then you know the authors know their shit. For those who don't know, this is basically HPC's "attention is all you need" but less overcooked: https://t.co/KWhx3NWPRY
Moore’s law still applies in the sense that the number of transistors in our processors increases exponentially. What broke around 2005 is Dennard scaling. Our clock frequencies are no longer increasing. But you don’t want to buy a processor from 2005: it is going to be much…
Moore’s law still applies in the sense that the number of transistors in our processors increases exponentially. What broke around 2005 is Dennard scaling. Our clock frequencies are no longer increasing. But you don’t want to buy a processor from 2005: it is going to be much… https://t.co/V65QQvnWHa
At end of 2027, AMD will release their MI500 Scale Up Mega Pod which may consist of 256 MI500 chips across three interconnected racks. The outer two racks will house 32 compute trays per rack, while the middle rack will hold 18 switch trays. That amounts to a total of 64 compute…
Post-Modern Cmake - From 3.0 to 4.0 - Vito Gamberini - C++Now 2025 youtu.be/K5Kg8TOTKjU #Coding #Cplusplus #Cpp #Programming
My #ACCU2025 talk is now up! A lot of work in this one: writing 2 versions (maybe more) of a ZX Spectrum emulator in C++. I had a blast & hope you will too following my journey of self-discovery: can this old dog learn some new (C++) tricks? Watch at: youtube.com/watch?v=jlt_fS…
@ryolu_ @cursor_ai everything eventually returns to Deiter Rams
GPU is GEMM Processing Unit :-)
It just feels like an awkward spot. If you want lots of memory+power, save up a bit more for the RTX Pro 6000. If you want to be hacky + fast, hook up a bunch of used 3090s/4090s together. If you want to be cool...get a bunch of TT Blackholes or something idk.
🦀 Rust is how we speed up Python now. The 2025 Python Language Summit revealed that 1 in 3 new PyPI native packages used Rust. Our survey results show that Rust usage for Python grew from 27% to 33%. 📊 From Polars to Pydantic to Granian – Rust is reshaping Python performance.…
Maybe other array folks can do better. The funny part is the initial C++ / Rust code is my code from a YouTube video I made 2 years ago. And the C code is cheating - it is using a constant time formula. youtube.com/watch?v=wGCWlI…
Maybe other array folks can do better. The funny part is the initial C++ / Rust code is my code from a YouTube video I made 2 years ago. And the C code is cheating - it is using a constant time formula. youtube.com/watch?v=wGCWlI… https://t.co/eyJ2qfWaMo
Except you should never use a dynamically resizable array, hashmap, or linked list. These are banned in my codebases. Learn static arrays, pools, and spsc ring buffer queues. Learn AoSoA and SoA. These are your fundamental data structures if you want good real-time performance.
Except you should never use a dynamically resizable array, hashmap, or linked list. These are banned in my codebases. Learn static arrays, pools, and spsc ring buffer queues. Learn AoSoA and SoA. These are your fundamental data structures if you want good real-time performance.
This could have various fundamental implications besides the speedup. Most importantly, most of the attention layer will become memory bound rather than compute bound, shifting the hardware emphasis further from systolic arrays to 3-D memory for inference. Super important.
This could have various fundamental implications besides the speedup. Most importantly, most of the attention layer will become memory bound rather than compute bound, shifting the hardware emphasis further from systolic arrays to 3-D memory for inference. Super important.
NVIDIA research just made LLMs 53x faster. 🤯 Imagine slashing your AI inference budget by 98%. This breakthrough doesn't require training a new model from scratch; it upgrades your existing ones for hyper-speed while matching or beating SOTA accuracy. Here's how it works:…
The number of "world’s fastest parallel file system"s out there is making my head spin. Or, in this case, "will be the world’s fastest." Going fast in one direction ("97 percent network utilization") isn't hard. Hitting the same numbers consistently in production is.
The number of "world’s fastest parallel file system"s out there is making my head spin. Or, in this case, "will be the world’s fastest." Going fast in one direction ("97 percent network utilization") isn't hard. Hitting the same numbers consistently in production is.
Yes it is!
More details on the GB10 Grace Blackwell Superchip by @NVIDIAAI as shown at @hotchipsorg #HC2025 - S-Dielet/S-Die (CPU, Memory Subsystem, etc.) - G-Dielet/G-Die (Blackwell-GPU) - TSMC 3nm (both) - Advanced 2.5D Packaging - 256b LPDDR5X-9400 (301 GB/s) hardwareluxx.de/index.php/news…
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