Digital Blocks Inc. @DigitalBlocksIP
Digital Blocks offers semiconductor Intellectual Property (IP) cores for System-on-Chip (SoC) ASSP, ASIC, and FPGA designers. digitalblocks.com Glen Rock, NJ USA Joined April 2010-
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#DisplayWeek2024- Digital Blocks DB9000 Display Controller IP in Verilog for SoC/ASIC/FPGA design teams continues to support a wide range of display resolutions, display technologies, and wide variety of end user applications, with licensing options for advanced display features
Greetings from Digital Blocks at Display Week 2023 in Los Angeles, CA
Orion has splashed down off the coast of Baja, California. Our spacecraft is home.
Greetings from Digital Blocks at Display Week in San Jose, CA
New IP: Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers from @DigitalBlocksIP design-reuse.com/sip/scatter-ga… #semIP
. @DigitalBlocksIP DB9000 TFT LCD and OLED Display Controller & Processor IP Application Leadership Advancements design-reuse.com/news/50913/dig… #semIP #semiconductor
Digital Blocks Display Controller is the leading Verilog IP for SoC, ASSP, ASIC, and FPGA designers, with extended features in video processing. digitalblocks.com/wp-content/upl…
Digital Blocks is attending the virtual DisplayWeek Aug 2020 conference where we are learning about advancements in display and imaging at the Symposiums and talking to display vendors in the virtual exhibit hall to learn the latest in display panel offerings. #DisplayWeek2020
. @DigitalBlocksIP #AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with targeted applications in DMA Streaming of Video and Data over PCIe or UDP/IP Network Interface. design-reuse.com/news/47453/dig… #semIP
Thanks for joining MIPI Alliance, @DigitalBlocksIP! We look forward to working with you.
Digital Blocks extends leadership of UDP/IP networking with Verilog Cores for 50 & 100 GbE UDP Protocol Hardware Stacks.
Digital Blocks extends leadership of UDP/IP networking with Verilog Cores for 50 & 100 GbE UDP Protocol Hardware Stacks.
Digital Blocks AXI4 Multi-Channel DMA Controller IP target AXI4 Interconnect backbone DMA transfers. With advanced features such as Scatter-Gather, 2D stride, coherency, security, and enhanced peripheral interface options. #ArmTechCon #semiIP #dma #riscv #soc
Digital Blocks MIPI I3C and I2C and SPI Controller Verilog IPs are the leading choice for ASIC/FPGA design teams interfacing to leading Sensors @SensorsExpo #MSDC19
Digital Blocks Display Controller is the leading Verilog IP for SoC, ASSP, ASIC, and FPGA designers. digitalblocks.com/2019/04/22/dig…
Digital Blocks celebrates National Engineers Week in New York City.
#HappyNewYear from semiconductor IP provider Digital Blocks. We have been a part of the NY Tech Scene for over 20 years. #TimesSquare #semiconductor #nyctech
Digital Blocks expands MIPI compliant I3C Controller family with I3C Slave Controller with APB Interface to local host CPU
Digital Blocks expands MIPI compliant I3C Controller family with I3C Slave Controller with APB Interface to local host CPU
Digital Blocks Subsystem Verilog IP target ARM, RISC-V, MIPS CPUs with best in class I2C, I3C, SPI, UART, CAN, LCD/OLED Display Controller, Graphics, Interrupt, DMA, TCP/UDP/RTP/MPEG-TS
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