FPGAParadox @FPGAParadox

FPGA/Emulation/ASIC/Formal (Static) verification/IP design. https://t.co/YMNMVKCHJr Internet Joined March 2021

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FPGAParadox @FPGAParadox

3 years ago

Reading the paper "Prophecy Made Simple" by Leslie Lamport and Stephan Merz, I kind of get how prophecy variables should be used and defined. I did this toy example to experiment with them, with an observational deterministic proof (of course liveness) an…lnkd.in/eFNASHaX

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FPGAParadox @FPGAParadox

3 years ago

Another one :D, but to be honest I took the "Jasper Formal Expert" like a year ago. I think I found a new hobby. lnkd.in/eyd_c4nj

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FPGAParadox @FPGAParadox

3 years ago

I just took the Jasper formal fundamentals exam, 50 questions, without even taking the course. I think it's not bad. lnkd.in/emNdQNUZ

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FPGAParadox @FPGAParadox

3 years ago

I tried both podman and Sylabs Singularity' to install Jasper. The idea was to port my work whenever I needed and as easy as possible. Podman is good and works great, but Singularity is just awesome. Here's an screenshot of how to bring/call the app (in…lnkd.in/e6jBQuye

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FPGAParadox @FPGAParadox

4 years ago

Understanding Tool Synthesis Behavior and Safe Finite State Machine Design arxiv.org/pdf/2108.04042…

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FPGAParadox @FPGAParadox

4 years ago

Poster How Efficient are Software Verifiers for Hardware? cs.utexas.edu/users/hunt/FMC…

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FPGAParadox @FPGAParadox

4 years ago

C-to-RTL verification has been enabled in JasperGold v2021.09. This app was previously hidden for beta adopters.

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FPGAParadox @FPGAParadox

4 years ago

Trust-hub security/property rule database: "This database is developed to support perform formal verification of SoC designs at RTL, Gate and Physical layout levels". trust-hub.org/#/data/Securit…

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FPGAParadox @FPGAParadox

4 years ago

Comparing OneSpin' Security Analysis App (reading the whitepaper on their website) vs JasperGold FSV (DAC paper) it seems that JG FSV is quite superior. What do you think? pure.tudelft.nl/ws/portalfiles…

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FPGAParadox @FPGAParadox

4 years ago

Enough for today I'll say.

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Axiomise @axiomise

4 years ago

Ep 48 axiomise.com/podcasts This week we talk to Prof. @vardi - one of the best-known names in computing & formal methods. In the 1st of the two episodes, we trace his journey from early years and talk logic, von Neumann, Backus, abstractions, LTL/CTL and #formalverification.

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FPGAParadox @FPGAParadox

4 years ago

Writing property transaction scoreboards: Transaction counters are great due the built-in forward progress checks that can be built on top of the main data transport property: if a counter is getting stuck for a period of time, a potential deadlock is uncovered.

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YosysHQ @YosysHQ

4 years ago

Always wanted to learn a bit of SVA? Our new app note 109 has got you covered: yosyshq.readthedocs.io/projects/ap109… Get in contact for an evaluation license!