Can We Replace a Program Counter with a Linear-Feedback Shift Register? Yes We Can! hackaday.com/2025/05/31/can…
@hackaday egad. IMHO that's a mite bit awful. I really ought to write up my recent hack and submit it.
To fully evaluate this idea I wish to see a comparison of instruction cycles needed for the CPU to execute conditional branches. I got the feeling it's saving on simplicity and transistors, yet sacrificing the performance... What about further platform features, like pre-fetching opcodes?
@hackaday Interesting idea but I think it would introduce new class of data leaks from timing side-channel. Whenever the logic would would branch, the cache misses would be worse than today. Address space randomization and program counter in sequence – the way it's done today – is better.
@hackaday I prefer cache hits than save an adder, thanks.
@hackaday LFSRs are great for addressing ‘sequential’ memory because an LFSR doesn’t have the carry delay problem that a variety of counters do. I used them in a waveform generator - you just load the table in the LFSR address sequence instead of incrementing.
