Search results for #SpinalHDL
#SpinalHDL is SOO op, I just need to learn it all #FPGA
Kathi talks about "Fuzz-testing of #SpinalHDL designs" at #MBMV2023. 👉 ics.jku.at/files/2023MBMV… #Fuzzing #EDA #hardware #verification
Presentation by Sallar Ahmadi-Pour from @agra_uni_bremen on "#SpinalHDL in Computer Architecture Research" youtu.be/VTP66adsem8 via @YouTube @unibremen #Scale4Edge @risc_v #riscv
Don't miss LeafLabs' Jeff Ciesielski presenting at the #SpinalHDL "Explore the SpinalHDL Landscape" webinar next Friday, December 16. He will be sharing how we're leveraging SpinalHDL to enable the rapid development of devices used for Neuroscience research!
You are interested in #fuzzing your #SpinalHDL design? Than have a look at "SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs" presented by Katharina Ruep tomorrow at European Test Symposium 2022. 👉 ics.jku.at/files/2022ETS_…
#DATE2021 - Sallar Ahmadi-Pour presenting at the University Booth on "MicroRV32: A #SpinalHDL based #RISC-V Implementation for #FPGAs" @agra_uni_bremen @DFKI #VerSys #scale4edge @BMBF_Bund @DateConference #DATEconference @risc_v #RISCv
Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH
See @antmicro’s very own #opensource Zynq Video Board running a #LiteX generated @risc_v softCPU written in #SpinalHDL, with MIPI CSI-2 camera input and HDMI output, running @ZephyrIoT #RTOS in an example of our open source IP core flow @mithro @enjoy_digital
#SpinalHDL looks like a really powerful language with great code generation performance.
#SpinalHDL looks like a really powerful language with great code generation performance.
Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL
SpinalHDLで書かれたFPGA向けRISC-Vプロセッサらしい / “GitHub - SpinalHDL/VexRiscv: A FPGA frien…” htn.to/NnkAkiV #spinalhDL #fpga #risc-v #hdl #cpu
SpinalHDL-Workshop at 33C3, today, 21:30, Hall C.3. events.ccc.de/congress/2016/… #SpinalHDL #33c3
New #SpinalHDL documentation : spinalhdl.github.io/SpinalDoc Help yourself : Try it for your next #FPGA #ASIC project instead of #VHDL #Verilog
