@hpcnotes The distinction between x86 as a architecture and x86 as a ISA is important. x86 is a mess, but the rise of the uop-based approach meant that the advantages and disadvantages of RISC vs CISC became a lot narrower. Honestly I think x86 is kind of disgusting but a lot of the ...
Well RISC-V is essentially a hybrid of MIPS and Alpha, and the mostly wart-free ISA (if you ignore the people yapping about how wrong the Cray-style SIMD is). x86 is the āmost RISC-ish CISC there isā while ARM is the āmost CISC-ish RISC there isā (the thing is heavily microcoded)
(Not a guru, just a reply guy with some cons) Ouch, not even a mention of POWER? Itās a niche arch now, but half of the other are completely dead, not even niche. :-) 32-bit ARM was a pain due to predicated instructions and a lack of architected ways to deprecate some old and overly complex instructions, but for HPC it was always a matter of 64-bit. RISC-Vās insistence on compressed instructions are awkward too and will start to hurt soon, but last attempt to start fixing it ended in fireworks and drama. Alphaās lack of ordering was a complete disaster for software.
It depends on what your goals are really. ARM or RISCV is the clear winner if you are trying to do a lot with little power. MIPS/SPARC are both good "down the middle" architectures. x86 is crap, but it was great in the 70s. It's power was that when others upgraded to new ideas, Intel stuck with crap, which already had loads of software while others had to do software from scratch, nuking their market share and delivering the win to x86... but... the Bible on architecture is Hennessy and Patterson... I haven't read it in quite a while, but I strongly remember them using x86 as examples of the wrong way to do things and using Alpha over and over on the best way to do things. Alpha was born for 64 bits. It was lean, mean, fast, superpipelined, superscaler, and elegant. It didn't win in the end but it was a thing of beauty. I've worked with all of them in one form or another and designed hardware around most of them. Alpha is the only one of the group that blew me away. The designers were superheros and went on to give AMD the lead over Intel and give Apple their custom ARM designs. The Alpha/StrongArm teams were top notch. ARM was great. StrongArm was unbelievable for the day.
@hpcnotes @samsoniuk The real question: 6502 or Z80! ā¤ļø
Define "best"... ARMv8 hits the best sweet spot in terms of - single length instructions with all that implies BUT - dense instructions (many instructions add a small modifier that's easily implemented, eg the CSEL variants) But that assumes your goal is fastest latency engine. It might be something else like minimal area... And ARMv8, if done again, would - clean up the bazillion different load/store variants - give NEON the best elements of SVE while maybe defining NEON as 256b wide.
@hpcnotes well, I think RISC-V is the winner because it is smaller and we can fit more cores per socket! take the case of GRVI Phalanx, with 1680 cores at 250MHz on a single VCU118! of course, different SW paradigm, kilocore approach! š„ carrv.github.io/2017/papers/grā¦
Mot a chip guru and not playing one on tv either, but can ask an ai (am interested and maybe this will cause experts to say how dumb ai is): Rankings and Rationale: 1. RISC-V: The best architecture in principle due to its minimalist, modular, and extensible design. Its open-source nature eliminates licensing barriers, and its clean ISA (no legacy baggage, fixed-length instructions, large register set) is ideal for both low-power and high-performance systems. The ability to add custom extensions (e.g., for AI or crypto) ensures future-proofing. However, its immaturity in high-performance microarchitectures is a minor drawback. 2. ARM: A close second, ARMās RISC design is highly efficient and scalable, with AArch64 providing a modern, clean 64-bit ISA. Its power efficiency and customization (via licensee extensions) are major strengths. However, proprietary licensing and multiple instruction sets (e.g., Thumb) add complexity compared to RISC-V. 3. Alpha: Alphaās early 64-bit RISC design was elegant and high-performing, with no legacy baggage. Its lack of modern extensions (e.g., SIMD) and limited evolution place it behind RISC-V and ARM. 4. SPARC: SPARCās register windowing and scalability are innovative, but its complexity and lack of modern enhancements make it less competitive. 5. MIPS: A clean RISC design but outdated by modern standards, with limited evolution and no significant advantages over ARM or RISC-V. 6. x86: Despite its performance optimizations, x86ās CISC complexity and legacy baggage make it less elegant than RISC alternatives. It excels in versatility but sacrifices simplicity and efficiency. 7. IA-64: EPICās innovative approach was hampered by compiler dependence and complexity, making it the least successful architecturally despite its potential. In my humble opinion arm will be the general purpose processor for the next generation considering non-technical things
@hpcnotes If being proprietary is a major con, RV is the winner, especially for the future. Other than that x64 is the best architecture because it has the most sophisticated implementation. Unfortunately you canāt ignore current success because thatās where the innovation is.
@hpcnotes If we're talking pure power, RISC-V takes it for me. It's pretty solid with the whole processing power vs drawbacks thing. By this I mean the rewards just outweigh the costs across board
@hpcnotes Purely architecturally, x86, ARM, RISC-V, MIPS, SPARC, and Alpha all converge on similar RISC-like microarchitectures today ā thereās no inherent ābest.ā The real differentiators are ecosystem maturity and openness. x86 and ARM dominate thanks to huge, stable software bases,
@hpcnotes In high performance CPUs it doesn't really matter. Each of the major architectures has advantages and disadvantages and for the most part the rectifiable ones are being rectified. What people attribute to architecture are often more a function of (past) implementation priorities.
@hpcnotes Depends on what you are optimizing for. Everything is a tradeoff
@hpcnotes Not a chip guru but Sparc64 for corecctness ? > [...] it is the most strict platform for detecting non-portable or buggy code. openbsd.org/want.html marc.info/?l=openbsd-bug⦠ieeexplore.ieee.org/document/46300⦠fujitsu.com/downloads/SPAR⦠anyone can elaborate further?