Leet Nothing @LeetNot
FHE enthusiast Joined December 2013-
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New post on a new upcoming #riscv extension: Zicond (public review still on-going): fprox.substack.com/p/zicond-risc-…
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New blog post on how to add a new #riscv instruction to the spike ISA simulator: fprox.substack.com/p/adding-a-new…
Fprox’s Substack: RISC-V Profiles fprox.substack.com/p/risc-v-profi…
Fprox’s Substack: Sneak peek at RISC-V RVA23(U64) profile fprox.substack.com/p/risc-v-profi…
Fprox’s Substack: RISC-V Vector Cryptography Extension (2/2) fprox.substack.com/p/risc-v-vecto…
Fprox’s Substack: RISC-V Vector Cryptography Extensions (1/2) fprox.substack.com/p/risc-v-vecto…
Leet Nothing retweeted
I start loosing track of all #riscv extensions. So, I created a little online tool to validate and explain RISC-V ISA string. rv.drom.io
Leet Nothing retweeted
I wrote the most naive CUDA matrix multiply and iteratively optimised it to ~80% of cuBLAS performance: siboehm.com/articles/22/CU…
Leet Nothing retweeted
@Gramner_ There's an excellent explanation from @pshufb here: 0x80.pl/articles/avx51…
New blog post: fprox.blogspot.com/2022/10/risc-v…, high level overview of @risc_v various register files (general purpose, floating-point and vector) #RISCV #isa
The last part of my blog series on @risc_v vector extension (RVV) is available: fprox.blogspot.com/2022/09/riscv-… . We conclude on RVV memory operations. #riscv #rvv
Leet Nothing retweeted
RISC-V heads to the stars! More details on @SiFive @risc_v cores being selected by NASA for future missions: businesswire.com/news/home/2022… #riscv
Part 5.1 of my blog series on @risc_v vector extension (RVV) is out: fprox.blogspot.com/2022/09/riscv-…, this time we cover some basic vector load/store operations (unit-stride, strided, indexed). #riscv
Leet Nothing retweeted
Spread the world about this year's #RISCV Global Summit Call for Proposals. We're accepting ideas for industry and technical sessions until Friday, Sept. 9 at 11:59 p.m. PT. Be sure to check out the guidelines and submit soon: hubs.la/Q01lnk8j0 #RISCVSummit #RISCVeverywhere
Part 4 of my blog post series on @risc_v vector extension (RVV 1.0) is out: fprox.blogspot.com/2022/08/isc-v-… We cover permute instructions. #RISCV
Part 3 of my blog post series on @risc_v vector extension (RVV) is out: fprox.blogspot.com/2022/08/risc-v… This time we cover masked operations and operations with masks. #RISCV
After investigating a surge of views of my latest blog post on #riscv vector extension: fprox.blogspot.com/2022/08/risc-v… it appears I was lucky enough to appear on r/asm: reddit.com/r/asm/comments… thank you for the boost. Stay tuned for part 3.
New blog post about #riscv vector extension (part 2) fprox.blogspot.com/2022/08/risc-v… (review of some of the main arithmetic instruction families).
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