Semiconductor Engineering @SemiEngineering

Deep Insights For The Tech Industry #semiconductor #semiEDA #AI #embedded #verification #lowpower #test #DataAnalytics #automotive #chipdesign #ICmanufacturing semiengineering.com Silicon Valley Joined September 2013

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Semiconductor Engineering @SemiEngineering

3 days ago

Power density is stressing board-level power delivery. semiengineering.com/voltage-regula… #powerdelivery #semiconductor #voltageregulator

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Semiconductor Engineering @SemiEngineering

3 days ago

The Limits Of AI’s Role In EDA Tools: AI is a set of algorithms capable of solving problems. But how relevant are they to the tasks that EDA performs? semiengineering.com/the-limits-of-… #semiEDA #AI #AgenticAI #VLSI #chipdesign

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Semiconductor Engineering @SemiEngineering

a week ago

Special report-->Glass Substrates Gain Momentum: Benefits increase with package size, but not all the kinks have been worked out semiengineering.com/glass-substrat… #semiconductor #glasssubstrates

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Semiconductor Engineering @SemiEngineering

2 weeks ago

Higher frequencies bring more complexity to every part of the network, from tiny antennas to powerful base station processors. semiengineering.com/new-antennas-a… #6G #wireless #semiconductor #edge #antennas

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Ed Sperling @Chip_Insider

2 months ago

Special Report: A 94-page research report on interconnect fundamentals for semiconductor engineers. semiengineering.com/on-die-and-in-… #semiconductor #interconnects

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Semiconductor Engineering @SemiEngineering

2 weeks ago

An expanding supply chain of dies feeding multi-die products is prompting chipmakers to reassess and expand on ways to instill trust from end to end. semiengineering.com/infusing-trust… #semiconductor #supplychain #traceability #ATE

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Semiconductor Engineering @SemiEngineering

2 weeks ago

Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference (@Cambridge_Uni , @imperialcollege et al.) semiengineering.com/hw-sw-co-desig… #AgenticAI #LLM #inferencing

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Semiconductor Engineering @SemiEngineering

2 weeks ago

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? semiengineering.com/the-demise-of-… #verification #semiconductor

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Semiconductor Engineering @SemiEngineering

3 weeks ago

Latest news: site licenses for chip equip; HBM4; Natcast layoffs; ASML’s big AI $; Arteris CEO on data movement in the AI age; Intel’s leadership; AI data center risks; MLPerf; DRAM drilldown; big shifts in memory hierarchy... semiengineering.com/chip-industry-… #semiconductor #semiEDA #AI

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Semiconductor Engineering @SemiEngineering

3 weeks ago

Contact resistance, or CRES, is one of those problems that most engineers prefer not to think about until it’s staring them in the face. semiengineering.com/the-hidden-cos… #semiconductor #CRES #ContactResistance #yield

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Semiconductor Engineering @SemiEngineering

3 weeks ago

Balancing Workloads In AI Processor Designs: Optimization and architecture definition are important, but there’s a downside to too much customization. semiengineering.com/balancing-work… #CPU #GPU #NPU #processors #AI #AIworkloads #AImodels

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Semiconductor Engineering @SemiEngineering

3 weeks ago

Semiconductor testing is undergoing multiple paradigm changes at once with the common goals of producing more known good die per month with low test cost. semiengineering.com/making-the-mos… #semiconductor #semiconductortest

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Semiconductor Engineering @SemiEngineering

4 weeks ago

Special Report: Cost of designing chips and IP will increase, and companies at fault for breaches will be liable for damages. semiengineering.com/security-requi… #cybersecurity #hardwaresecurity #CyberResilience #ZeroTrust #semiconductor #CRA #EU

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Semiconductor Engineering @SemiEngineering

3 weeks ago

How DRAM works, why there are different flavors, the impact of cooling new solutions in denser configurations, and ongoing issues involving the security of data. semiengineering.com/the-evolution-… #DRAM #HBM #GDDR @rambusinc #LPDDR

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Semiconductor Engineering @SemiEngineering

4 weeks ago

Latest: Cadence’s $3.1B buy; chip design to tapeout program; PWC’s IC analysis; new packaging consortium; high-NA EUV; revenue reports; tough new security regulations; India’s buildout; GenAI for EDA; cloud vs edge gaming; AI chip design.. semiengineering.com/chip-industry-… #semiconductor

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Semiconductor Engineering @SemiEngineering

4 weeks ago

A new technical paper titled “The Future of Memory: Limits and Opportunities” was published by researchers at Stanford University semiengineering.com/a-fundamental-… #DRAM #SRAM #memoryhierarchy #2Dscaling #semiconductor @Stanford

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Semiconductor Engineering @SemiEngineering

4 weeks ago

6G Line-Of-Sight Repeaters, Dots, And Reflections: Private networks and city-wide simulations show how 6G providers will reach edge devices via repeaters, small cell radios, and reflections. semiengineering.com/6g-line-of-sig… #6G #edgecomputing #edgedevices