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Zip CPU @zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification zipcpu.com Gisselquist Technology, LLC, Joined January 2017
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Zip CPU @zipcpu

a day ago

@lel0uch_vb Thank you, you are right, I grabbed the wrong section of the file. This would be where I see multiple drivers. Both STATUS and DATA appear multiply driven.

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Zip CPU @zipcpu

3 days ago

What do you think ... is 1'b00 an error?

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Zip CPU @zipcpu

3 days ago

Customer: If I adjust your file order, your regression simulations fail I'm simulating w/ Cadence. This is weird. If I don't delete the cache between simulation runs, the bug is masked. Hmmm ...

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Zip CPU @zipcpu

a week ago

We have a winner! After 9 days and 16 hrs (232 hrs total), Boolector has beaten Z3, Yices2 *and* CVC5. Much to my surprise, Z3 had the fastest basecase solver, but Boolector remains the fastest induction solver (for this test case).

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Zip CPU @zipcpu

3 weeks ago

We have a winner! After 9 days and 16 hrs (232 hrs total), Boolector has beaten Z3, Yices2 *and* CVC5. Much to my surprise, Z3 had the fastest basecase solver, but Boolector remains the fastest induction solver (for this test case). https://t.co/3IyDVQk6Kn

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Zip CPU @zipcpu

2 weeks ago

When it comes to learning digital design, I would argue there's only a small palette of tools that need to be learned. These can all be learned in a semester. Getting good with them? That could take a lifetime. What do you think?

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Zip CPU @zipcpu

2 weeks ago

Now, with a new UPS, the solver race is back on. Four solvers in contention on one proof. We'll see who wins.

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Zip CPU @zipcpu

3 weeks ago

Now, with a new UPS, the solver race is back on. Four solvers in contention on one proof. We'll see who wins. https://t.co/HSzLYI1XpR

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Zip CPU @zipcpu

2 weeks ago

I'm thinking of writing an article on how to do "digital clock division". Sure, you can create a "new" clock signal, but the trick is to avoid transitioning any logic on that new digital signal, while keeping the IP transitioning on the original system clock

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Zip CPU @zipcpu

3 weeks ago

My Dad, a CrayOS developer, once tried to write a language he called "D". I'm not sure if it ever made it out of his office. It certainly never caught on.

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Dave W Plummer @davepl1968

3 weeks ago

My Dad, a CrayOS developer, once tried to write a language he called "D". I'm not sure if it ever made it out of his office. It certainly never caught on.

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Zip CPU @zipcpu

3 weeks ago

Second test failed when the power browned out after 7 hrs. I'm now browsing UPS battery power on Amazon ...

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

Second test failed when the power browned out after 7 hrs. I'm now browsing UPS battery power on Amazon ...

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

See ... this is the problem I have with most of the commercial tools I have access to ... I have access to the tools, but not the courseware and ... I can't figure out where to start with their documentation. At least with open source tooling you can google any thing you need to…

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Steever @beaversteever

3 weeks ago

See ... this is the problem I have with most of the commercial tools I have access to ... I have access to the tools, but not the courseware and ... I can't figure out where to start with their documentation. At least with open source tooling you can google any thing you need to…

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Zip CPU @zipcpu

3 weeks ago

Well, the first test was a failure. Power's been going out here regularly every day in the late afternoon. When the CPU is on high power, the UPS can't keep up and everything shuts down. All I know so far is that the proof will take longer than 5hrs independent of the solver.

zipcpu Profile Picture

Zip CPU @zipcpu

3 weeks ago

Well, the first test was a failure. Power's been going out here regularly every day in the late afternoon. When the CPU is on high power, the UPS can't keep up and everything shuts down. All I know so far is that the proof will take longer than 5hrs independent of the solver.

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