天 Oğuz Meteer 天 @[email protected] @BitlogIT
Digital ASIC designer | PhD candidate @UTwente | Writer at the BitLog technology blog | #FPGA and #ASIC connoisseur | Twitch: https://t.co/MUib6EPK3s bitlog.it Joined December 2016-
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天 Oğuz Meteer 天 @[email protected] retweeted
I’ve completed my year-long journey to becoming a published author in electrical engineering. Mastering FPGA Chip Design: For Speed, Area, Power, and Reliability is now part of the Elektor Academy Pro series and available in both print and eBook formats: elektor.com/products/maste…
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I'm supposed to be on vacation in Türkiye right now, but I'm still going to meet people here and talk about chip design 😂 Work never ends haha. But it's nice to meet new people 😊
I was featured in an article as an alumnus of @UTwente 😁 utwente.nl/en/stories/stu…
天 Oğuz Meteer 天 @[email protected] retweeted
This is the moment @rej's open source Z80 woke up and said hello! After Zilog’s April 2024 announcement, ReJ quickly taped out a drop-in replacement to preserve retrocomputing and legacy systems. Taped out on TT07, it's a landmark in democratizing chip design.
Who do you think is its Oshi?
Who do you think is its Oshi? https://t.co/6GsTCNqGrR
Two polygons is two whole polygons more than my GPU :D Nice work!
Two polygons is two whole polygons more than my GPU :D Nice work!
OK, so I just recently discovered @BABYMETAL_JAPAN and they are doing a concert here in the Netherlands May 13th. Guess where I'm going? 😁
天 Oğuz Meteer 天 @[email protected] retweeted
Check out our repository and book for Wally shop.elsevier.com/books/risc-v-m… - an OpenHW core. You can easily simulate a program with wsim (e.g., wsim rv64gc --elf fir CPI=1.43) with any ELF file - all files included in the GitHub repo. Works w/Verilator/Questa/VCS and AMD FPGAs/SoCs.
天 Oğuz Meteer 天 @[email protected] retweeted
I'm going to start a regular weekly stream on #opensource silicon. Topics will include design, verification, #fpga, openlane, formal, #tinytapeout, #ASIC bringup, chip validation. If you're interested, please let me know what days / times work for you: doodle.com/meeting/organi…
天 Oğuz Meteer 天 @[email protected] retweeted
Imagine, a gate level simulation of an ASIC running in your browser! znah.net/tt09/ This interactive simulation by @zzznah actually lets you look inside a digital design as it’s running! It’s a cellular automata and he taped it out on @tinytapeout 9!
天 Oğuz Meteer 天 @[email protected] retweeted
My friend Atıl is missing. If you’re in Spain, particularly in Barcelona, and happen to see him, please call:
天 Oğuz Meteer 天 @[email protected] retweeted
Introducing a SKY130 ROM compiler project I've been working on for a while. youtu.be/MlqDm_Kg0u8 This is just a quick intro to the project with following episodes diving into all the tech details of the design.
天 Oğuz Meteer 天 @[email protected] retweeted
A small step for a hobby logic designer, but a giant leap for @tinytapeout. The first official RISC-V uLinux ASIC, yes, ASIC, you heard that right, is operational and functional. Just dabbling in chip design as a hobbyist. Haha, what an awesome achievement! Thanx to @matthewvenn…
天 Oğuz Meteer 天 @[email protected] retweeted
🚨Amnesia Generation. The Internet will lose over 500,000 books. The Internet Archive has been ordered to delete them. The Internet Archive is appealing and essential for libraries to lend, preserve ensure access to out-of-print books. Sign a protest: change.org/p/let-readers-…
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arturo182 is on Blues... @arturo182
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