PDVL @PDVLcc
PDVL is an aspect oriented and transaction level Programming, Design and Verification Language. Free & #OS HW\SW #SystemVerilog #Verilog #VHDL #UVM #SVA #PSL cloudx.cc Munich, Good Old Bavaria Joined September 2017-
Tweets78
-
Followers95
-
Following102
-
Likes143
It'll be interesting how you tackle it. Best wishes and good luck.
It'll be interesting how you tackle it. Best wishes and good luck.
Open access papers till June for "The Fourth ACM SIGPLAN History of Programming Languages Conference, Co-Vital with PLDI 2012": hopl4.sigplan.org dl.acm.org/toc/pacmpl/202…
Inspiring open accessible 2-pager available for LATTE ’21 (Workshop on Languages, Tools, and Techniques for Accelerator Design): capra.cs.cornell.edu/latte21/
Trying to count electrons (or holes if I can detect some) as they fly by (almost) at the speed of light. Cycle accurate power consumption measurements of #RISCV cores. Oh boy, it’s not going to work. Wish me luck.
FREE 1020-page PDF eBook covers the #Mathematics of #DeepLearning d2l.ai via @KirkDBorne CC: @mvollmer1 @FmFrancoise @YvesMulkers @Fabriziobustama @jenstirrup @andi_staub #AI #MachineLearning #BigData #Analytics #NeuralNetworks #DataScience #Algorithms #Books
“Test-Case Reduction via Test-Case Generation: Insights From the Hypothesis Reducer” – @DRMacIver, @afd_icl. #ecoop20 #research #paper ➡️ 2020.ecoop.org/details/ecoop-…
The best free introductory course on formal verification I have ever seen: intrologic.stanford.edu/public/index.p…
Languages of the Future: Mandarin vs. JavaScript by @GoBomberbot link.medium.com/Gsgma9bB77
The Coq Workshop 2020 will be held online on July 5-6. Everyone is welcome to join! Please see this Discourse post for more detail: coq.discourse.group/t/call-for-par…
The REMS-@deep_spec workshop (part of @PLDI 2020) will be held online on June 15-16th: pldi20.sigplan.org/home/rems-deep… Registration is free but it closes on June 5th!
Kilocore ? LOL. Kilothreads is the new threat in town ! 64 CUBE-V cores on a KCU116 => 1024 dynamically interleaved threads => ~30 GIPS (Giga Instructions Per Seconds) ! #RISCV
Is doxygen (still) the preferred tool for C++ project documentation? Thanks for your thought. I'm preparing an open source release for my PDVL to SystemVerilog converter tool written in C++. Need to add documentation for it.
Wow that's something. Though I'm not a fan of the language itself, obviously. bluespec.com/2020/01/06/blu…
It is with great pleasure to announce the release of the open source Arduissimo project on github. Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programs on the ARTY board (XC7A35T). #riscv #shp #cubev github.com/cloudxcc/Ardui…
2nd WOSET Workshop on Open-Source EDA - Breakfast Bytes - Cadence Blogs - Cadence Community shar.es/a37Jd7
We would like to invite you to contribute to #abz2020's case study. We welcome submissions that use any formalism (not just ASM, Alloy, B, TLA, VDM and Z). For more information visit abz2020.uni-ulm.de/case-study #abz2020
And now at full speed! 64 continuously blinky threads on a RISC-V (RV32iMC) based Quad-Core MP-SoC (16 interleaved threads each core) on the ARTY FPGA board. Reaching ~620 MIPS. #threatening #SHP #riscv
The program for the 30th International Workshop on Rapid System Prototyping (RSP) is out. Looking forward to a great week in NY. conferences.telecom-bretagne.eu/rsp-symposium/…
Thoreth @ThorethyFyVJt
10 Followers 547 Following
Colby Tang @ColbyTang
93 Followers 3K Following
Wellsun Tech @Peng2022Ruby
217 Followers 2K Following SMT assembly‖OEM/ODM/JDM‖ Accept sample‖ small batches and large batches‖E-mail:[email protected]‖WhatsApp:+86 18617199069‖
Victor Suarez Rovere @suarezvictor
2K Followers 809 Following Software, Electronics, DSP. Ready for consulting work. [email protected] / @[email protected]
linuxbest @linuxbest
66 Followers 638 Following
PipelineC (fosstodon.... @pipelinec_hdl
858 Followers 126 Following https://t.co/iJcPcgcbrj PipelineC hardware description language
Vimal Manivannan @vimalyohen
296 Followers 4K Following Verification Engineer #semicon-professional.
JaguarLV @jaguar_lv
186 Followers 4K Following
Vartan Polodyan @VarPol
188 Followers 6K Following
yanchinglun @yanchinglun1
19 Followers 280 Following
*Roy = NULL @null_roy
212 Followers 4K Following Embedded Software Dev | Tech Enthusiast | Embedded Linux, C/C++ by day, Rust by night
FPGAParadox @FPGAParadox
397 Followers 166 Following FPGA/Emulation/ASIC/Formal (Static) verification/IP design. https://t.co/YMNMVKCHJr
JART @JART_TECH
14 Followers 647 Following
Mudita Man @MuditaMan
92 Followers 4K Following
Sylvain Lefebvre @sylefeb
5K Followers 412 Following Researcher-maker-hacker focusing on Computer Graphics with a #retro, #fpga gaming twist. Enjoys #3dprinting and #electronics. Created @iceslapp and #Silice.
cunty bastard @triplekunt
26 Followers 142 Following
LegUp Computing (now ... @LegUpComputing
197 Followers 141 Following We provide an HLS integrated development environment tool that enables engineers to compile C/C++ software into Verilog targeting Microchip FPGA devices
HighLevelSynthesis @HighLevelSynth1
400 Followers 588 Following Designing digital systems and accelerating functions with #HLS for #Xilinx #FPGAs Mohammad Hosseinabady PhD.
oemsecrets.com @oemsecrets
3K Followers 4K Following https://t.co/k90jmYYb3f is a leading comparison engine offering marketing and development solutions for the electronics industry.
Singh, Satinder Paul @PaulSatinder
1K Followers 4K Following Chief Technical Officer | Strategist in Semiconductor Technology domain | VLSI/SoC/ASIC/IC (Chip) Design Specialist
Nikola Tesla @seanjensengrey
434 Followers 5K Following
Greg Zuro @softboyled
162 Followers 539 Following All comments are “hypothetical” and not intended to convey facts
Sierra-Pacific Techno... @SierraPacificT1
432 Followers 2K Following
Hipólito Guzmán @hipolitoguzman
486 Followers 1K Following Professor at @unisevilla. Design, Verification and Fault Tolerance of digital circuits and systems. FPGAs, CPLDs, VHDL, SystemVerilog, UVM, FT-Unshades.
Priyanshu Mishra @Priyans57411485
1K Followers 5K Following SoC Verification Engineer | Processor Architecture Verification (RISC-V/Arm/x86) VLSI | AI/ML in Chip Design Research | DIY
king @kingshuk1000
8 Followers 203 Following
Vince @Vino_tl
171 Followers 2K Following
★ STMAN ★ 🏳️... @stmanfr
3K Followers 1K Following Crypto-Anarchist Researcher on IC & kernels Security Flows, P2P & Mesh Networks, FPGA & Microprocessors Architectures. Cyberspaces Theorician. Hardware Hacker.
Kenny Umenthum @umenthum
151 Followers 763 Following Open source, hardware, simulation, verification, FPGA, HLS, compilers, synthesis, HDLs he/him
𝔻𝕠𝕜𝕒 @idoka_ru
504 Followers 664 Following Hardware Imagineer | Digital IC Design Engineer | Editor of ASIC/FPGA digest.
Kasai @thekasailife
946 Followers 8K Following …. ⚓ Riverside, California👉 Chicago👉 Hampton Roads...
Rikesh Kishore Sahay @sahayrikesh
196 Followers 2K Following |#Engineer| |#MTech #VLSI #Design| |#IETE (E&T) #NewDelhi| |#OfficialName 🔄 #Mukesh| |Views r personal| |RTs≠Endorse| |🇮🇳|
Mohamad Krayem 👶 @Mhd_Krayem
801 Followers 4K Following Ph.D. Eng. -SoC Architect | automotive application -#5G #5GCore -Microelectronics & Computer Science -ASIC/FPGA -HW/SW -DTPM management | MP-SoC -ML & AI
AMIQ EDA @amiq_eda
3K Followers 848 Following An EDA company. Software that enables hardware design and verification engineers to increase the speed and quality of chip development.
Nikhil @Nick_s_Nair
17 Followers 187 Following Silicon Design Engineer | RCBian Forever | Tip for life: Adapt or Perish
Terminus Electronics @terminelectro
2 Followers 19 Following
PLDI @PLDI
5K Followers 974 Following The ACM SIGPLAN Conference on Programming Language Design and Implementation. Official hashtag this year: #PLDI2025. Tweets by @konskallas and @lastland0
Diego @dhdezr73
902 Followers 814 Following I was born one day, and since that day I have never stopped working. What is that thing everyone calls burnout?
Henry @henryf2009
175 Followers 2K Following Fullstack FPGA, Impedance nuts, Time nuts, Volt nuts, Signal nuts...
Epic Maps 🗺️ @theepicmap
1.2M Followers 6 Following Educational and informative world Maps 🗺️. We do not own any content posted. Dm for removal/credit.
He @shengwenLeong
4 Followers 279 Following
Leo Lampropoulos @LeoLambro
1K Followers 623 Following Assistant Professor at UMD | Programming languages, random testing, and formal verification
cocotb @cocotbnews
288 Followers 1 Following cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
Formal Land 🌲 @FormalLand
1K Followers 2K Following Security for Web3, through formal verification 🚀 Ethereum, Solana, Sui 🔍 Solidity, Rust, zero-knowledge. DM us to ensure your code is safe!
Shraddha Barke @shraddha_96
677 Followers 887 Following Senior Researcher @MSFTResearch | program synthesis, AI4Code, large language models, Human-AI | PhD from @ucsd_cse, @Theteamatx, @BITSPilaniGoa.
Nadia Polikarpova @polikarn
4K Followers 291 Following Associate prof @ucsd_cse. Building tools for program verification and synthesis.
Harshitha @Harshit49678822
25 Followers 63 Following
Toby Murray @tobycmurray
1K Followers 632 Following Go find me at @tobycmurray.bsky.social. Assoc Prof at @UniMelb and @cis_unimelb cyber lead; @DSI_VIC Director; @UniofOxford DPhil (@HertfordCollege); He/him
Patrick Lehmann @PaebbelsLemmi
85 Followers 34 Following Vice-Chair of the IEEE P1076 Working Group (VHDL Analysis and Standardization Group); VHDL Expert; FPGA Technology Trainer; Open Source IP Core Maintainer
FPGAParadox @FPGAParadox
397 Followers 166 Following FPGA/Emulation/ASIC/Formal (Static) verification/IP design. https://t.co/YMNMVKCHJr
Joachim Breitner @nomeata
2K Followers 1 Following Has a thing for abstraction. Haskeller, Computer Scientist. Dances tango, swing and blues. Stand-up comedian and paraglider. 🦣 https://t.co/9Sjz02h8dL
Sylvain Lefebvre @sylefeb
5K Followers 412 Following Researcher-maker-hacker focusing on Computer Graphics with a #retro, #fpga gaming twist. Enjoys #3dprinting and #electronics. Created @iceslapp and #Silice.
OpenMP ARB @OpenMP_ARB
2K Followers 64 Following The OpenMP Architecture Review Board (ARB) standardizes directive-based multi-language high-level parallelism that is performant, productive and portable.
Singh, Satinder Paul @PaulSatinder
1K Followers 4K Following Chief Technical Officer | Strategist in Semiconductor Technology domain | VLSI/SoC/ASIC/IC (Chip) Design Specialist
Ben Delaware @GhostofBendy
1K Followers 309 Following Professor at @PurdueCS; dad; occasional cancer fighter🎗️. Tweets about programming languages and formal methods, but mostly bird pictures.
Vartan Polodyan @VarPol
188 Followers 6K Following
Allen Baker @althebaker43
43 Followers 337 Following I'm an aspiring computer and electrical engineer.
Vince @Vino_tl
171 Followers 2K Following
Jean-François Monest... @jmonesti
90 Followers 718 Following Senior Software Engineer @ST_World, supporting the STxP70 CPU architecture, implementations, and associated tools.
Nikola Tesla @seanjensengrey
434 Followers 5K Following
reto @oter
570 Followers 5K Following
Camilo Rojas @RojasMilo
167 Followers 288 Following https://t.co/TRFPL9TdEz. Student, Open-V Digital Circuit Designer. Member of @onchipUIS @UIS
Hipólito Guzmán @hipolitoguzman
486 Followers 1K Following Professor at @unisevilla. Design, Verification and Fault Tolerance of digital circuits and systems. FPGAs, CPLDs, VHDL, SystemVerilog, UVM, FT-Unshades.
lulinchen @lulin_chen
10 Followers 88 Following
Ben Reynwar @benreynwar
30 Followers 236 Following
Andres Mancera @_andres_mancera
31 Followers 118 Following Engineer at @RealityLabs | Former @fungible_inc, @SpaceX & @JuniperNetworks | @UDelaware & @UniJaveriana grad | I turn coffee into SystemVerilog code
Rahul Deshpande @rahulpande01
28 Followers 519 Following Engineer (Micro-Electronics) | A-Political | Geo-Politics | Disruptive Technology | Economics | Public Policy | Chess | RISC V Revolution
Mudita Man @MuditaMan
92 Followers 4K Following
Hitika Sardana @SardanaHitika
40 Followers 56 Following Indian / Emulation Engineer / Reading and knowing things is the best thing you can do for yourself.
Rohit Reddy @Rohit_red_y
17 Followers 300 Following
Kenny Umenthum @umenthum
151 Followers 763 Following Open source, hardware, simulation, verification, FPGA, HLS, compilers, synthesis, HDLs he/him
king @kingshuk1000
8 Followers 203 Following
Tamon Sadasue @tamon_sadasue
119 Followers 167 Following ネットワークプロトコル・セキュリティ処理や暗号のハードウェア（FPGA/ASIC向け)開発が今のお仕事。発言は所属を代表します。
Silexica, a Xilinx co... @silexica
381 Followers 323 Following Silexica was acquired by Xilinx in June 2021. Follow @XilinxInc to learn how we make adaptive computing accessible to software developers.
Clément Pit-Claudel @cpitclaudel
819 Followers 814 Following EPFL (@ICepfl) assistant professor. Compilers, verification, hardware, & IDEs. Also lots of Emacs modes. Previously PhD @MIT and AppSci @AWS.
The Rocq Prover @CoqLang
2K Followers 55 Following This account is no longer used. Follow us on Mastodon at @[email protected] (https://t.co/YQ7JNBex1u) instead.
Muzaffer Kal @🏡 �... @MuzafferKal_
2K Followers 6K Following Chips: ASIC, FPGA. CV/ML. Duck pictures by the lake. Some bread making.
Fermat's Library @fermatslibrary
775K Followers 4 Following A platform for illuminating academic papers. We annotate and share a paper every week. Save, annotate and share papers with anyone: https://t.co/0o2Pls3jmoTrends for United States
You might like
