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RISC-V.chip.haus @RISCVchip

News and information about the RISC-V instruction set architecture and its implementations, brought to you by @ChipHaus. en.wikipedia.org/wiki/RISC-V Joined January 2019
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RISC-V.chip.haus retweeted
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linuxdevices @linuxdevices

4 years ago

SiFive RISC-V Rack Cluster and custom PC power up with HiFive Unmatched: SiFive and AB Open demoed a “SiFive RISC-V Rack Cluster” that runs Linux on four of SiFive’s RISC-V U74 based HiFive Unmatched boards. AB Open and Future Computing recently announce… ift.tt/3EGqsa0

RISC-V.chip.haus retweeted
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The Register @TheRegister

4 years ago

Chatter around GPUs for RISC-V is growing reg.cx/42gr

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RISC-V.chip.haus @RISCVchip

4 years ago

“RISC-V Business: Testing Gaming and More on the HiFive Unmatched from @SiFive” (@Level1Techs, 14 min.) 📺 youtu.be/lgatG_i8UMg

RISC-V.chip.haus retweeted
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Mouser Electronics @MouserElec

5 years ago

Register for a LIVE panel discussion with @MicrochipTech and @crowd_supply exploring the future of RISC-V this Tuesday! Details: mou.sr/risc-v-webinar #webinar #RISCV #IoT #5G

RISC-V.chip.haus retweeted
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Lup Yuen Lee 李立源 @MisterTechBlog

5 years ago

#Mynewt #RISCV is Hardcoded for SiFive FE310 ... Here's our fix for #PineCone #BL602 @thepine64 lupyuen.github.io/articles/mynewt

RISC-V.chip.haus retweeted
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Bruno Levy @BrunoLevy01

5 years ago

#femtorv32 #riscv core for #FPGA: implemented basic ELF support. I'm using it at two different places: * in femtOS, that can now directly run elves from an SDCard. * to generate 'bare metal' firmwares by directly converting an ELF into verilog / readmemh() github.com/BrunoLevy/lear…

RISC-V.chip.haus retweeted
BrunoLevy01 Profile Picture

Bruno Levy @BrunoLevy01

5 years ago

#femtorv #riscv core for #fpga: added a tutorial for the ECP5 evaluation board github.com/BrunoLevy/lear… Coming next: the FOMU ! (after the largest of my collection, the tiniest !)

RISC-V.chip.haus retweeted
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Masayuki@FPGA開発日記 @dev_msyksphinz

5 years ago

"Hardware description language Chisel & Diplomacy Deeper Dive" my presentation video in RISC-V Study meetup online Dec.18 is uploaded! #RISCV youtube.com/watch?v=92rULS…

RISC-V.chip.haus retweeted
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OGAWA, Tadashi @ogawa_tter

5 years ago

=> "MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect", @LucaBeniniZhFe , to appear at DATE21 (arXiv, Dec 5, 2020) arxiv.org/abs/2012.02973 @pulp_platform 256 fast RV32IMA (#RISCV) “Snitch” cores Shared L1 scratchpad memory pool, 5cycles 700MHz GF 22FDX

RISC-V.chip.haus retweeted
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OGAWA, Tadashi @ogawa_tter

5 years ago

@LucaBeniniZhFe @pulp_platform => "A Tiny #RISCV Floating-Point Unit", L. Bertaccini, ETH Zurich, RISC-V Summt 2020, Dec 8 PDF pulp-platform.org/docs/riscv2020… @pulp_platform Integer Snitch core is optimized for area Fast to Tiny-FPU Trading area for latency Snitch, arXiv, Oct 8 arxiv.org/abs/2002.10143 @LucaBeniniZhFe

RISC-V.chip.haus retweeted
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OGAWA, Tadashi @ogawa_tter

5 years ago

=> "MEEP's emulated accelerator architecture", Nov 15, 2020 meep-project.eu/media/news/mee… VAS Accelerator Tile Shared L2: 4 MB Core #RISCV Vector Processing Unit via OVI Systolic Arrays "The Future HPC will be open", Prof. M. Valero, Keynote, IEEE HPCC 2020

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OGAWA, Tadashi @ogawa_tter

5 years ago

=> "MEEP's emulated accelerator architecture", Nov 15, 2020 meep-project.eu/media/news/mee… VAS Accelerator Tile Shared L2: 4 MB Core #RISCV Vector Processing Unit via OVI Systolic Arrays "The Future HPC will be open", Prof. M. Valero, Keynote, IEEE HPCC 2020 https://t.co/8ZmOBBPPmx

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RISC-V.chip.haus @RISCVchip

5 years ago

Project Oberon 2013 on RISC-V 🛠 github.com/solbjorg/obero… 💬 news.ycombinator.com/item?id=254970… Cf. github.com/sam-falvo/proj…

RISC-V.chip.haus retweeted
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OGAWA, Tadashi @ogawa_tter

5 years ago

=> RVfpga: Using A Commercial RISC-V Processor to Teach Computer Architecture, RISC-V Global Forum, Spe 3, 2020 09:58 youtube.com/watch?v=LrbIvD… static.sched.com/hosted_files/r… developed by Imagination Sep 2 imaginationtech.com/news/press-rel… A-Series GPU Firmware processor

ogawa_tter Profile Picture

OGAWA, Tadashi @ogawa_tter

5 years ago

=> RVfpga: Using A Commercial RISC-V Processor to Teach Computer Architecture, RISC-V Global Forum, Spe 3, 2020 09:58 youtube.com/watch?v=LrbIvD… static.sched.com/hosted_files/r… developed by Imagination Sep 2 imaginationtech.com/news/press-rel… A-Series GPU Firmware processor https://t.co/bWU1D8cN1R

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RISC-V.chip.haus @RISCVchip

5 years ago

“What is a system-on-chip (SoC), and why do we care if they are open source?” (@bunniestudios, 2020-11-10) 👉 bunniestudios.com/blog/?p=5971 💬 news.ycombinator.com/item?id=250390… 💬 lobste.rs/s/cafrvh/what_…

RISC-V.chip.haus retweeted
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Hackster.io @Hacksterio

5 years ago

.@SipeedIO plans $12.50 Linux-capable RISC-V dev board family based on the XuanTie C906: bit.ly/35fGgl0

RISC-V.chip.haus retweeted
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PULP Platform @pulp_platform

5 years ago

As the #RISC-V summit is approaching, this week we would like to introduce PULP's speakers. On Tuesday, 8 December 2020 at 11:00 am we will have Luca Bertaccini presenting "A Tiny RISC-V Floating-Point Unit" tmt.knect365.com/risc-v-summit/…

RISC-V.chip.haus retweeted
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AB Open @ABOpenLtd

5 years ago

A Look at the RISC-V PC from SiFive. abopen.com/news/a-look-at… #RISCV #FOSSi

RISC-V.chip.haus retweeted
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TechCrunch @TechCrunch

5 years ago

SiFive’s new PC is bringing open-source computing closer to reality tcrn.ch/3oNQBfI by @DannyCrichton

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RISC-V.chip.haus @RISCVchip

5 years ago

“A Plan 9 C Compiler for RISC-V RV32GC and RV64GC” (Richard Miller, 2020-10-19, 33 min.) 📺 youtu.be/LHJqdXGb0uc

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